[Q-e-developers] computer hardware future trends

[Alex Balboa]

Dear Honorable Quantum ESPRESSO developers,I will be attending a computer hardware requirements meeting around October 20, 2016 (9:00 am – 1:00 pm) specifically to providerecommendations/suggestions for hardware improvements path forward regardingcomputational chemistry codes and algorithms.  Is there anything special that Quantum ESPRESSO is working on future releases inQE 5.5.0(?) that may be of value to mention so we anticipate futurecomputational chemistry needs?  Icurrently use the following computer architectures on the Cray XC40(http://ark.intel.com/products/81060/Intel-Xeon-Processor-E5-2698-v3-40M-Cache-2_30-GHz)

xxx

Max Memory Size (dependent on memory type)             768 GB

Memory Types DDR41600/1866/2133

Max # of Memory Channels        4

Max Memory Bandwidth             68GB/s

# of Cores           16

# of Threads       32

Processor Base Frequency           2.30GHz

Max Turbo Frequency   3.60GHz

Cache    40 MBSmartCache

Bus Speed           9.6GT/s QPI

# of QPI Links     2

xxx

512 GB node:


 
=====  Processorcomposition  =====

Processor name    :Intel(R) Xeon(R)  E5-2698 v3

Packages(sockets) : 2

Cores             :32

Processors(CPUs)  :32

Cores per package : 16

Threads per core  :1


 
=====  Cachesharing  =====

Cache   Size            Processors

L1      32  KB         no sharing

L2      256 KB          no sharing

L3      40  MB         (0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30)(1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31)


 
Mem:    516419Mtotal,    10844M used,   505574M free,       73M buffers

Swap:    62499Mtotal,        0M used,    62499M free,     2550M cached

xxx

768 GB node:


 
=====  Processorcomposition  =====

Processor name    :Intel(R) Xeon(R)  E5-2698 v3

Packages(sockets) : 2

Cores             :32

Processors(CPUs)  :32

Cores per package : 16

Threads per core  :1


 
=====  Cachesharing  =====

Cache   Size            Processors

L1      32  KB         no sharing

L2      256 KB          no sharing

L3      40  MB         (0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30)(1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31)


 
Mem:    774979Mtotal,    20882M used,   754096M free,      120M buffers

Swap:    62499Mtotal,        0M used,    62499M free,     8200M cached


 
Does  QE 5.5.0 (?) exploit any L1, L2 and/or L3cache that may need to be increased ?


xxx

One such future CPU architecture for example is(http://ark.intel.com/products/93790/Intel-Xeon-Processor-E7-8890-v4-60M-Cache-2_20-GHz)


 
# of Cores           24

# of Threads       48

Processor Base Frequency           2.20GHz

Max Turbo Frequency   3.40GHz

Cache    60 MB

Bus Speed           9.6GT/s QPI

# of QPI Links     3

Max Memory Size (dependent on memory type)             3.07 TB

Memory Types DDR4-1333/1600/1866DDR3-1066/1333/1600

Max # of Memory Channels        4

Max Memory Bandwidth             102GB/s

xxx

Thus one can go from 768 GB up to 3.07 TB memory size, 40MB to 60 MB L3 Cache and 16 cores/32 threads to 24 cores/48 threads on a"big memory" single node. 


 
Thanks,

alex

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